1. Field of the Invention
The present invention relates in general to a semiconductor connecting device and a method for making the same, and more particularly to improvements in reducing cell areas.
2. Detailed Description of the Prior Art
For convenience, description is provided of the structure of a DRAM cell in which a bit line is connected with a drain electrode in advance of a capacitor being connected with a source electrode.
Generally, a gate electrode and source/drain electrodes are formed in one active region, followed by the formation of a bit line to be connected with the drain electrode. For the sake of forming a charge storage electrode contact in the source electrode, the bit line is positioned above a device separation insulating film which is between the source electrodes, in such a way that the bit line is not placed above the source electrode or is overlapped with the source electrode only in a minimal part.
A conventional method for making the above bit line is described with reference to a few figures.
Referring initially to FIG. 1, there is a schematic plan view showing only important mask layers. For example, while reference mark A designates an active region mask, B, C, D, E, and F designate a first bit line contact mask, a pad mask, a second bit line mask, a bit line mask, and a charge storage electrode contact mask, respectively. As shown in this figure, the first bit line contact mask B is electrically connected with the second bit line contact mask D via the pad mask C.
For a more detailed description, FIGS. 2A to 2C are referenced in, which there are schematic cross-sectional views illustrating the steps for fabricating a DRAM cell according to a conventional method, respectively, taken generally through section line A--A' of FIG. 1.
First, as shown in FIG. 2A, on a predetermined portion of a semiconductor substrate 1, an active region and a device separation insulating film 2 are formed, followed by the formation of a gate electrode (not shown), a source electrode (not shown) and a drain electrode 3 over the active region. Next, an interlayer insulating film 4 is formed on the resulting structure, and then, a first bit line contact is formed by use of the first bit line contact mask B, followed by the formation of a conductive material pad 5'. At this time, the conductive material pad 5' is formed in such a way to cover the first bit line contact enough and extend partially the device separation insulating film.
Subsequently, another interlayer insulating film 6 is formed, as shown in FIG. 2B.
Finally, using the second bit line contact mask D, a second bit line contact is formed on a predetermined portion of the conductive pad 5' which is placed over the device separation insulating film 2. Following this, a bit line 7' is formed in the second bit line contact, as shown in FIG. 2C. At this time, via the second bit line contact, the bit line 7' is connected with the conductive pad 5' which is, in turn, connected with the drain electrode 3 via the first bit line contact. As a result, the bit line 7' is electrically connected with the drain electrode 3.
When the bit line is connected with the drain electrode in such conventional method, the bit line is not positioned above the source electrode on which the charge storage electrode is to be formed later. The conventional method and accompanied structure, however, requires complicate steps to be undertaken in order to interconnect the drain electrode and the bit line. In addition, the device separation insulating films between which the conductive material pad is formed occupy much room in the cell, so as to reduce the usable room in the cell when scaling a semiconductor down.